# Analog-to-digital converter An **analog-to-digital converter** (ADC) is an electronic system that turns a continuously varying quantity, usually a [[Voltage|voltage]] or an [[Electric_current|electric current]], into a sequence of numbers. It does two things to the [[Analog_signal|analog signal]]: it takes [[Sampling_(signal_processing)|samples]] at regular instants, and it rounds each sample to the nearest of a finite set of levels, the step called [[Quantization_(signal_processing)|quantization]]. The result is a stream of binary words, the raw material of [[Digital_signal_processing|digital signal processing]] and, once framed and serialised, of [[Pulse-code_modulation|pulse-code modulation]]. A [[Digital-to-analog_converter|digital-to-analog converter]] performs the reverse operation. A converter is rated first by its resolution, the number of bits in each word, and by its sample rate. Resolution fixes the smallest step and with it the quantization error, which for a busy full-scale signal behaves like noise with a [[Signal-to-noise_ratio|signal-to-noise ratio]] of about `6.02*B + 1.76 dB` for `B` bits. Sample rate fixes the highest frequency the words can represent, half the rate; anything above that line folds back into the band as [[Aliasing|aliasing]], which is why an [[Anti-aliasing_filter|anti-aliasing filter]] stands in front of nearly every converter and why many run faster than the application needs, a practice called [[Oversampling|oversampling]]. Converters are built in a handful of architectures, from the flash converter that decides every bit at once to the [[Delta-sigma_modulation|delta-sigma]] converter that trades a crude quantizer for a very high rate; almost all are [[Integrated_circuit|integrated circuits]]. The page's primary microsim, *Analog-to-digital conversion*, lets the reader set the bit depth, sample rate, frequency and amplitude of a test waveform and watch the sample dots, the quantized staircase and the binary words change together as the sketch prints the step and the ideal signal-to-noise ratio. A second sketch, *Analog-to-digital converter*, runs a successive-approximation conversion one bit per clock cycle against an input the reader sets by clicking. ## Characteristics ### Resolution A converter of `n` bits has `2^n` output codes, and its resolution, the input change that moves the output by one code, is the range divided by `2^n`.[^dyer32] Dyer and Davis work the arithmetic for a 0–5 V input at 3 bits: eight codes spaced 0.625 V apart, so that 2.36 V is reported as 2.5 V, an error of 5.9322 percent, and the largest possible error is half a step, ±0.3125 V. The top code sits one step below full scale, at 4.375 V, because the codes begin at zero; at 8 bits the step shrinks to 0.0195 V and the top code rises to 4.98 V.[^dyer33] An input that overruns the range clips, which is worse than wasted resolution.[^dyer36] Two conventions for the step are in use: Dyer and Davis divide the range by `2^n`, Stiber, Stiber and Larson by `2^n − 1`, so that the top code lands exactly on full scale.[^stiber60] The primary microsim prints `Δ = 2/2^B` for its ±1 span, 0.1250 at the default `B = 4`, but the code that draws its staircase reconstructs each sample as `code/(2^B − 1)`, the second convention. The difference between the input and the level chosen for it is the quantization error. It is bounded by half a step,[^dyer34] and for a busy input it takes every value in that band about equally often, behaving like noise with a root-mean-square value of `Q/√12`,[^dyer38] about 0.29 of one least significant bit (LSB).[^stiber59] For a sine wave filling the whole range the ratio of signal power to this noise power is `SNR = 6.02*n + 1.76 dB`,[^dyer39] the formula the sketch's HUD prints: 25.8 dB at the default 4 bits, 49.9 dB at 8. The noise model fails for a slow or constant input, whose error is a fixed number rather than a random one; a small sine that crosses only a few levels becomes a staircase whose harmonics are [[Distortion|distortion]], not noise.[^stiber59] Dither is the cure: a random signal of about one LSB added ahead of the quantizer makes the code toggle between neighbours in proportion to where the input lies between them, decorrelating the error from the signal. The primary sketch has no dither; at `B = 2` its four-level staircase makes the effect plain. ### Accuracy Resolution says how finely a converter divides its range; accuracy says how close the division is to the ideal. The departures are an offset, a gain error and nonlinearity: integral nonlinearity (INL) is the largest deviation of the transfer curve from a straight line, and differential nonlinearity (DNL) the largest deviation of any single step from one LSB, a DNL below −1 LSB meaning a code that never appears. Fiore's 10-bit ATmega328P converter is specified at 0.5 LSB of integral nonlinearity and ±2 LSB of absolute accuracy,[^fiore134] so its last bit or two are not absolute. The second sketch's ladder is ideal, and the INL and DNL panel its header promises is not drawn. ### Jitter The sampling instants of a real converter are not perfectly regular. A timing error `δt` on a signal changing at rate `dx/dt` produces an amplitude error `δt · dx/dt`, and for a full-scale sine of frequency `f` with root-mean-square jitter `t_j` the signal-to-noise ratio is limited to `−20*log10(2π f t_j)`, a standard result: 1 ps of jitter on a 100 MHz sine caps the ratio near 64 dB, roughly a 10-bit budget, however many bits the converter has. The clock of a fast converter is therefore an analog signal. ### Sampling rate The [[Nyquist–Shannon_sampling_theorem]] sets the floor: a signal whose spectrum vanishes above `fmax` is recovered exactly from samples taken at any rate `fs > 2*fmax`.[^dyer48] Half the rate is the sampler's [[Nyquist_frequency|Nyquist frequency]], above which a component is recorded as a lower one; Tiberius and Mulder's 11 Hz cosine is recovered perfectly at 30 samples per second and turned into a 1 Hz cosine at 10.[^tib112] The primary sketch reproduces the effect on its own scale. Its window is one second wide, so `f_s` samples appear across it and the test waveform completes `f_sig` cycles; the HUD prints `f_Nyquist = f_s/2` and raises a red ALIASING banner when `f_sig` exceeds it. The waveform carries a third harmonic at `3*f_sig` with 15 percent of the fundamental's amplitude, which the banner ignores: at the defaults, 3 Hz sampled at 20 Hz, the harmonic at 9 Hz sits just under the 10 Hz Nyquist frequency, and at `f_sig = 4 Hz` it already folds while the banner stays dark. The theorem applies to the highest component present, which is why the [[Anti-aliasing_filter|anti-aliasing filter]] ahead of the converter, a [[Low-pass_filter|low-pass filter]] cutting off below the Nyquist frequency, is not optional. Oversampling means sampling well above `2*fmax`. The quantization noise power `Q²/12` does not depend on the rate but is spread over the band from zero to `fs/2`, so a [[Digital_filter|digital filter]] that keeps only the band of interest removes the noise above it, and reducing the rate afterwards, called decimation, discards nothing of value; each doubling of the rate buys 3 dB, half a bit. Fiore's ATmega328P shows the other end of the scale: it converts at about 15,000 samples per second at full resolution,[^fiore134] and the Arduino `analogRead()` call built on it takes about 100 µs, about 10,000 readings per second.[^fiore136] ## Common features Most converters share a set of supporting parts around the quantizer. A sample-and-hold circuit, a switch and a [[Capacitor|capacitor]], freezes the input for the duration of the conversion, since an input that moves while the bits are decided yields a code that belongs to no instant. The second sketch demonstrates the need by omitting the circuit: in its AUTO SWEEP mode the input keeps drifting while the register settles, and the `|error|` readout in the bottom HUD can exceed one LSB where a held input would leave it below one. A reference voltage sets the full-scale range and therefore the LSB. The ATmega328P's converter divides its reference by 1,024, so a 5 V reference gives a step of 4.9 mV;[^fiore136] its AREF pin has an internal resistance of 32 kΩ, so a reference fed through a series [[Resistor|resistor]] of `R` kilohms arrives as `V_AREF = V_ext*32/(32 + R)`, and 2.5 V through 5 kΩ becomes 2.2 V at the pin.[^fiore138] A clock paces the conversion, 13 cycles of a 50–200 kHz ADC clock in the same part, 25 for the first,[^fiore135] and control [[Sequential_logic|logic]], usually a small [[Finite-state_machine|state machine]], starts it, flags its end and presents the result as a [[Binary_number|binary number]]: unsigned for a unipolar converter such as the ATmega's,[^fiore134] offset binary or two's complement for a bipolar one. ## Types ### Flash A flash converter compares the input against every level at once: a ladder of `2^B − 1` [[Resistor|resistors]] across the reference produces every threshold, one comparator sits at each, and logic turns the resulting thermometer code into a `B`-bit word. Conversion takes one clock, but the comparator count doubles with every bit, which confines the architecture to about 8 bits and the highest speeds. ### Successive approximation The successive-approximation register (SAR) converter performs a binary search with one comparator and an internal [[Digital-to-analog_converter|digital-to-analog converter]]. The register sets its most significant bit, the converter turns the trial word into a voltage, and the comparator reports whether that voltage exceeds the input; if it does, the bit is cleared, otherwise it stays, and the next bit is tried the same way until, after `B` clock cycles, the register holds the code. The second sketch animates exactly this loop: with the default `B = 4` and its 16 levels the register settles in 4 cycles, and at `B = 8` its 256 levels take 8, the `T_conv = B cycles` of the HUD. Its comparator keeps a bit only when the trial voltage does not exceed the input, so the code it returns is the highest level not above `V_in` and the error is one-sided, between zero and one LSB; production converters add a half-step offset to centre it. The HUD writes the trial voltage as `V_DAC = V_ref·Σ(b_i·2^(B−1−i))/2^B`, but the code divides by `2^B − 1`, so the top code reaches `V_ref` exactly. The ATmega328P's converter is of this type,[^atmega] and the architecture is the usual choice from 8 to 18 bits. ### Ramp-compare A ramp-compare converter runs a counter that drives a digital-to-analog converter, or an analog integrator that ramps, upward from zero until a comparator finds that the ramp has passed the input; the count at that moment is the result. It is simple and inherently monotonic, but the worst-case conversion takes `2^B` clocks. ### Dual-slope integrating The dual-slope converter integrates the input for a fixed time, then switches the integrator to a reference of opposite sign and counts clock cycles until the output returns to zero. The second interval is proportional to the input, and because both slopes share the same resistor, capacitor and clock, their tolerances cancel. Accuracy is high and speed is low, the combination a digital voltmeter wants. ### Tracking A tracking converter keeps an up/down counter driving a digital-to-analog converter, with a comparator telling the counter which way to step. Once locked it follows the input one LSB per clock, but a step takes up to `2^B` cycles to catch. ### Pipelined A pipelined converter chains several coarse stages, each of which resolves a few bits, reconverts them, subtracts the result from its input and amplifies the residue for the next stage. Every stage works on a different sample at the same time, so the throughput is one sample per clock while the latency is several clocks; it is the architecture of most converters running from tens of millions to billions of samples per second, in [[Radar]] receivers and oscilloscopes. ### Delta–sigma A delta-sigma converter runs a quantizer of one or a few bits inside a [[Negative_feedback|negative-feedback]] loop clocked at many times the final sample rate. The loop integrates the difference between the input and the fed-back output, which pushes the quantization noise toward high frequencies, where a digital [[Low-pass_filter|low-pass]] decimation filter removes it. [[Delta-sigma_modulation]] has its own article; the architecture dominates audio and precision measurement. ### Voltage-to-frequency A voltage-to-frequency converter turns the input into a pulse train whose rate is proportional to it, a form of [[Frequency_modulation|frequency modulation]], and a counter tallies the pulses over a fixed gate time. The count averages over that time, which makes the method slow, noise-tolerant and easy to isolate. ### Wilkinson The Wilkinson converter charges a capacitor to the peak of an input pulse and discharges it at constant current while a counter runs; the discharge time, and so the count, is proportional to the pulse height. Because every channel is one clock period wide, the differential linearity is excellent, and the design became the standard of nuclear pulse-height analysis. It is named for Denys Wilkinson, who described a ninety-nine-channel analyser built on the principle in 1950.[^wilk50] ## Applications A few applications have shaped their own techniques. A time-stretch converter handles signals too fast for any electronic converter by slowing the waveform first, typically by impressing it on a light pulse spread in a dispersive medium. Interleaved ADCs reach a high rate by running `M` converters at `fs/M` each, clocked at staggered phases, and merging their outputs; any mismatch of offset, gain or timing between channels appears as spurious tones at multiples of `fs/M`. The sliding scale method improves differential linearity by adding a known offset, changed for every conversion, at the analog input and subtracting it digitally from the result, so that one input voltage is converted by many different codes and their width errors average out. Any physical quantity can be converted once a [[Sensor|sensor]] or [[Transducer|transducer]] has turned it into a voltage, and resistance and capacitance can be measured without one: a microcontroller charges the unknown capacitor, or charges a known one through the unknown resistor, and counts the time until a comparator threshold is crossed, a ramp-compare converter with the unknown in the ramp. Music recording made high-resolution converters commonplace: a microphone signal is converted at a rate such as the 44.1 kHz of Downey's audio examples, where a 10 ms segment holds 441 samples,[^downey70] and the word length sets the [[Dynamic_range|dynamic range]]: Stiber, Stiber and Larson budget 59, 83 and 107 dB at 8, 12 and 16 bits, a convention 9.03 dB above the sine formula.[^stiber60] [[Audio_signal_processing|Audio]] converters are almost all of the delta-sigma type. Digital signal processing in the wider sense is the converter's whole downstream: [[Digital_filter|digital filters]], the [[Discrete_Fourier_transform]] computed by the [[Fast_Fourier_transform|fast Fourier transform]], and the software-defined receiver, in which the converter moves ever closer to the antenna and the mixing and filtering of the [[Superheterodyne_receiver|superheterodyne receiver]] are done in arithmetic. Scientific instruments use every architecture: the dual-slope converter of the multimeter, the pipelined converter of the oscilloscope, the Wilkinson converter of the pulse-height analyser, and the banks that read out a [[Charge-coupled_device|charge-coupled device]] or a [[Sonar|sonar]] array. Displays fed analog video digitise each colour channel at the pixel clock. ## Electrical symbol In circuit diagrams the converter is a rectangle divided by a diagonal line, the analog input side marked with a small sine wave or the letter A and the digital output side with the number sign or the letter D, as in the international [[Electronics|electronic]] symbol sets. In block diagrams a plain box labelled ADC or A/D is at least as common. Neither sketch on this page draws the symbol; both open the box. ## Testing A converter is tested statically and dynamically. The static tests feed a slow ramp or a signal of known probability density and count how often each code appears; a code that appears too often or too seldom has the wrong width, and the histogram yields the offset, gain error, DNL, INL and any missing codes. The dynamic tests apply a pure [[Sine_wave|sine]] near full scale and take the [[Fast_Fourier_transform|fast Fourier transform]] of the output, with a [[Window_function|window]] applied unless the record holds a whole number of cycles; from the spectrum come the [[Signal-to-noise_ratio|signal-to-noise ratio]], the total harmonic distortion, the signal-to-noise-and-distortion ratio (SINAD) and the spurious-free dynamic range. The effective number of bits inverts the ideal formula, `ENOB = (SINAD − 1.76)/6.02`,[^dyer39] and tells how many bits are actually delivered at that frequency; the primary sketch's ideal quantizer would test to exactly its nominal `B`. The IEEE standard for converter terminology and test methods defines these quantities and their measurement.[^ieee1241] ## Microsims The primary microsim, *Analog-to-digital conversion*, shows the three stages side by side. The left panel, Analog + Samples, draws one second of a test waveform, a sine at `f_sig` with a 15 percent third harmonic, with a green dot at every sample instant and an amber dot at the level each sample is rounded to; the right panel, Quantized Reconstruction, holds each amber level until the next sample, the staircase of a [[Zero-order_hold|zero-order hold]]. Four sliders set Bits B (1–8, default 4), f_s (2–80 Hz, default 20), f_sig (1–20 Hz, default 3) and A, the amplitude as a fraction of full scale (0.20–1.00, default 0.80). The bottom HUD prints B, the number of levels, the step Δ, f_s, f_Nyquist and the ideal `SNR_q ≈ 6.02·B + 1.76 dB`, raises the ALIASING banner when `f_sig > f_s/2`, and lists the binary codes of the first samples in the window. The model is ILLUSTRATIVE: the waveform is synthetic, the quantizer is ideal and the code's step convention differs from the printed Δ. A three.js companion renders this concept in depth. *Try:* Set A to 1.00 and Bits B to 1, then step B upward one bit at a time; watch the two-level staircase at the right become a recognisable copy of the wave by B = 4 while SNR_q climbs from 7.8 dB to 25.8 dB and on to 49.9 dB at B = 8, then drag f_s down from 20 Hz and watch the red ALIASING banner appear as f_s falls below 6 Hz. The second microsim, *Analog-to-digital converter*, opens the successive-approximation converter. The left panel, SAR Convergence, shows the input `V_in` as a horizontal line on a normalised 0–1 voltage scale and the trial voltage `V_DAC` stepping toward it one bit at a time; the right panel, SAR Register + Binary Search, shows the register bits from MSB to LSB, the bit under test highlighted, and the path through the binary search tree. Bits B runs from 2 to 8, default 4, and Speed sets how many frames each bit takes (1–30, default 12). Space pauses, m toggles between AUTO SWEEP, in which the input drifts slowly up and down, and MANUAL, in which a click or drag in the left panel sets `V_in`, and r restarts the conversion. The bottom HUD prints B, the number of levels, the LSB as `1/(2^B − 1)`, the current `|error|` and the cycle count, and on completion the status line reads Done with the code and the voltage. A finished conversion holds its code until r is pressed, the panel is clicked or B is changed; the Conversions completed counter does not advance. *Try:* Press m for MANUAL, click about two-thirds of the way up the left panel and watch the four bits resolve in turn, V_DAC jumping to 0.533, dropping back when 0.800 overshoots, and finishing within one LSB below the line with Done: code = 9 / 15 or a neighbour; then set Bits B to 8, press r, and count the eight cycles it now takes while the LSB readout shrinks from 0.0667 to 0.0039. ## Wikipedia : Wikitube **Strict pair:** [Wikipedia](https://en.wikipedia.org/wiki/Analog-to-digital_converter) : [Wikitube](https://en.wikitube.io/wiki/Analog-to-digital_converter) Skeleton mirrored at revision 1375083942. Prose, emphasis and the microsims are Wikitube's own. ## See also - [[Pulse-code_modulation]] - [[Digital_signal_processing]] - [[Anti-aliasing_filter]] - [[Quantization_(signal_processing)]] - [[Oversampling]] - [[Digital-to-analog_converter]] - [[Delta-sigma_modulation]] - [[Sampling_(signal_processing)]] - [[Nyquist–Shannon_sampling_theorem]] - [[Aliasing]] - [[PORTAL_Signal_Processing]] ## Notes Both sketches are ILLUSTRATIVE: the primary quantizes a synthetic waveform with an ideal quantizer and no dither, and its code divides the span by `2^B − 1` while its HUD prints `2/2^B`; the second has an ideal ladder, a truncating comparator and no sample-and-hold, and the transfer-function panel its header describes is not drawn. Page numbers in the references are PDF pages of the open editions. ## References [^dyer32]: Dyer, J.; Davis, C. *Measurement and Instrumentation: An Introduction to Concepts and Methods*. 1st ed., 2020, p. 32 (PDF page): 2^n codes and resolution = range/2^n. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/measurement-and-instrumentation-an-introduction-to-concepts-and-methods . CC BY-NC-SA. [^dyer33]: Dyer, J.; Davis, C. *Measurement and Instrumentation: An Introduction to Concepts and Methods*. 1st ed., 2020, pp. 33-34 (PDF pages): Example 2.2, a 0–5 V range at 3 bits (0.625 V per step, 2.36 V read as 2.5 V, 5.9322 percent error, ±0.3125 V maximum error, top code 4.375 V) and at 8 bits (0.0195 V per step, top code 4.98 V). Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/measurement-and-instrumentation-an-introduction-to-concepts-and-methods . CC BY-NC-SA. [^dyer34]: Dyer, J.; Davis, C. *Measurement and Instrumentation: An Introduction to Concepts and Methods*. 1st ed., 2020, p. 34 (PDF page): the quantization error is bounded by ±0.5 of the resolution. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/measurement-and-instrumentation-an-introduction-to-concepts-and-methods . CC BY-NC-SA. [^dyer36]: Dyer, J.; Davis, C. *Measurement and Instrumentation: An Introduction to Concepts and Methods*. 1st ed., 2020, p. 36 (PDF page): clipping from too narrow a range is worse than wasted resolution. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/measurement-and-instrumentation-an-introduction-to-concepts-and-methods . CC BY-NC-SA. [^dyer38]: Dyer, J.; Davis, C. *Measurement and Instrumentation: An Introduction to Concepts and Methods*. 1st ed., 2020, pp. 38-39 (PDF pages): the rms quantization noise Q/√12. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/measurement-and-instrumentation-an-introduction-to-concepts-and-methods . CC BY-NC-SA. [^dyer39]: Dyer, J.; Davis, C. *Measurement and Instrumentation: An Introduction to Concepts and Methods*. 1st ed., 2020, pp. 39-40 (PDF pages): SNR = 6.02 N + 1.76 dB for a full-scale sine. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/measurement-and-instrumentation-an-introduction-to-concepts-and-methods . CC BY-NC-SA. [^dyer48]: Dyer, J.; Davis, C. *Measurement and Instrumentation: An Introduction to Concepts and Methods*. 1st ed., 2020, pp. 48-49 (PDF pages): the sampling condition fs > 2 fmax. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/measurement-and-instrumentation-an-introduction-to-concepts-and-methods . CC BY-NC-SA. [^stiber59]: Stiber, M.; Stiber, B.; Larson, E. *Signal Computing: Digital Signals in the Software Domain*. 2020, p. 59 (PDF page): the uniform error model, σ = 1/√12 LSB ≈ 0.29 LSB, and its failure for a slow or constant input. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/signal-computing-digital-signals-in-the-software-domain . CC BY-SA. [^stiber60]: Stiber, M.; Stiber, B.; Larson, E. *Signal Computing: Digital Signals in the Software Domain*. 2020, pp. 60-61 (PDF pages): the LSB as range/(2^n − 1); quantization budgets of 59, 83 and 107 dB at 8, 12 and 16 bits on the span/σ convention; the quiet-passage budget. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/signal-computing-digital-signals-in-the-software-domain . CC BY-SA. [^tib112]: Tiberius, C.; Mulder, M. *Engineering Signal Analysis: From Fourier to filtering - Theory*. 2026, pp. 112-115 (PDF pages): an 11 Hz cosine sampled at 30 Hz is recovered exactly; sampled at 10 Hz it aliases to 1 Hz. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/engineering-signal-analysis-from-fourier-to-filtering-theory . CC BY. [^fiore134]: Fiore, J. *Embedded Controllers Using C and Arduino*. 2nd ed., 2018, p. 134 (PDF page): the ATmega328P converter's 10 bits, about 15 kS/s, 0.5 LSB integral nonlinearity, ±2 LSB absolute accuracy and unipolar input. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/embedded-controllers-using-c-and-arduino-2e . CC BY-NC-SA. [^fiore135]: Fiore, J. *Embedded Controllers Using C and Arduino*. 2nd ed., 2018, p. 135 (PDF page): 13 ADC clocks per conversion, 25 for the first, from a 50–200 kHz ADC clock; the result registers, ADCL read before ADCH. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/embedded-controllers-using-c-and-arduino-2e . CC BY-NC-SA. [^fiore136]: Fiore, J. *Embedded Controllers Using C and Arduino*. 2nd ed., 2018, p. 136 (PDF page): LSB = Vref/1024 = 4.9 mV at 5 V; analogRead() takes about 100 µs, about 10,000 readings per second. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/embedded-controllers-using-c-and-arduino-2e . CC BY-NC-SA. [^fiore138]: Fiore, J. *Embedded Controllers Using C and Arduino*. 2nd ed., 2018, pp. 136-138 (PDF pages): the AREF divider V_AREF = V_ext·32/(32 + R) with R in kΩ; 2.5 V through 5 kΩ gives 2.2 V. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/embedded-controllers-using-c-and-arduino-2e . CC BY-NC-SA. [^downey70]: Downey, A. *Think DSP: Digital Signal Processing in Python*. 2012, p. 70 (PDF page): a 0.01 s segment at 44.1 kHz holds 441 samples. Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/think-dsp-digital-signal-processing-in-python . CC BY-NC. [^atmega]: Microchip Technology. *ATmega48A/PA/88A/PA/168A/PA/328/P megaAVR Data Sheet*. 2018, Analog-to-Digital Converter chapter: the ATmega328P features a 10-bit successive approximation ADC. https://www.microchip.com/en-us/product/ATmega328P [^wilk50]: Wilkinson, D. H. "A stable ninety-nine channel pulse amplitude analyser for slow counting". *Mathematical Proceedings of the Cambridge Philosophical Society*, vol. 46, no. 3, 1950, pp. 508-518. [^ieee1241]: Institute of Electrical and Electronics Engineers. *IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters*. IEEE Std 1241-2010, revision of IEEE Std 1241-2000, 2010. ## Further reading - Dyer, J.; Davis, C. *Measurement and Instrumentation: An Introduction to Concepts and Methods*, 1st ed. (2020). Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/measurement-and-instrumentation-an-introduction-to-concepts-and-methods - Fiore, J. *Embedded Controllers Using C and Arduino*, 2nd ed. (2018). Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/embedded-controllers-using-c-and-arduino-2e - Stiber, M.; Stiber, B.; Larson, E. *Signal Computing: Digital Signals in the Software Domain* (2020). Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/signal-computing-digital-signals-in-the-software-domain - Tiberius, C.; Mulder, M. *Engineering Signal Analysis: From Fourier to filtering: Theory* (2026). Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/engineering-signal-analysis-from-fourier-to-filtering-theory ## External links - *Analog-to-digital conversion*, the primary sketch: https://editor.p5js.org/sciencenibber/full/8xKJaOCM8 (fork: https://editor.p5js.org/sciencenibber/sketches/8xKJaOCM8) - *Analog-to-digital converter*, the successive-approximation sketch: https://editor.p5js.org/sciencenibber/full/eV8CWZA1F (fork: https://editor.p5js.org/sciencenibber/sketches/eV8CWZA1F) <!-- Hubs: Signal_processing. Portals: PORTAL_Signal_Processing. Signal Processing portal wave 1 · 2026-09-17 · drafted. -->