# List of HDL simulators ## Links (Wikipedia order) <!-- injected from _registry/childlinks/List_of_HDL_simulators.json (2026-07-30T02:09:12Z) --> `AMD` · `ARC_(processor)` · `ARM_Cortex-M` · `Achronix` · `Aldec` · `Altera` · `Application-specific_integrated_circuit` · `Arm_Holdings` · `C_to_HDL` · `Cadence_Design_Systems` · `Chisel_(programming_language)` · `Complex_programmable_logic_device` · `Cypress_PSoC` · `ELLA_(programming_language)` · `Field-programmable_gate_array` · `Hardware_acceleration` · `Hardware_description_language` · `High-level_synthesis` · `Icarus_Verilog` · `Infineon_Technologies` · `Intel` · `Intellectual_property` · `Lattice_Semiconductor` · `Mentor_Graphics` · `MicroBlaze` · `Microchip_Technology` · `ModelSim` · `NXP_Semiconductors` · `Ngspice` · `Nvidia` · `Open-source_hardware` · `OpenCores` · `OpenRISC` · `Power_ISA` · `Programmable_Array_Logic` · `Programmable_logic_array` · `Programmable_logic_device` · `Property_Specification_Language` · `RISC-V` · `Reconfigurable_computing` · `SPICE` · `Siemens` · `Silvaco` · `Soft_microprocessor` · `Synopsys` · `SystemC` · `SystemVerilog` · `System_on_a_chip` · `Texas_Instruments` · `Unified_Power_Format` · `VHDL` · `VHDL-AMS` · `Verilator` · `Verilog` · `Verilog-A` · `Verilog-AMS` · `Virtex_(FPGA)` · `Xilinx` > Summary stub · part of Systems Engineering · [Wikipedia source](https://en.wikipedia.org/wiki/List_of_HDL_simulators) ## Summary This list enumerates HDL simulators, software packages that simulate designs written in hardware description languages such as Verilog, SystemVerilog, and VHDL. These simulators let engineers verify the logical behavior of digital circuits before committing them to silicon or FPGAs. Notable tools include ModelSim/Questa, Verilator, and the open-source GHDL and Icarus Verilog. HDL simulation is a core step in digital design verification. ## Key points - Enumerates HDL simulators - Simulate Verilog, SystemVerilog, and VHDL designs - Verify digital logic before fabrication - Examples include ModelSim, Verilator, and GHDL - Core to digital design verification ## Relation to Systems Engineering HDL simulation is the verification activity for digital hardware subsystems, supporting the systems-[[Engineering|engineering]] goal of validating components before integration. ## Sources - [List of HDL simulators — Wikipedia](https://en.wikipedia.org/wiki/List_of_HDL_simulators) Back to Systems Engineering --- <!-- SEMIOTIC-PROFILE:START --> ## Semiotic profile > *The semiotic universals this article invokes, machine-derived from the crossref — **unverified** (born so). Populated 2026-07-06 for the Systems room.* **Universals (2):** 🟡 system (6) · 🟢 discretization (5) **Enter by sign:** Systems Semiotic Gateway · Alphabetum · Icon Registry · ← Systems Portal <!-- SEMIOTIC-PROFILE:END --> ## Wikipedia : Wikitube **Strict pair:** [Wikipedia](https://en.wikipedia.org/wiki/List_of_HDL_simulators) : [Wikitube](https://en.wikitube.io/wiki/List_of_HDL_simulators) ## Previous hub tags Tree parent: [[Systems_engineering]]. Legacy hubs: none. --- *Sources: 1 legacy note. Minted wave 1, 2026-07-30 (v1.6 order).*