Phase-locked_loop - Wikiparency

# Phase-locked loop A **phase-locked loop** (PLL) is a negative-feedback [[Control_system|control system]] that continuously adjusts a local oscillator until its phase tracks the phase of an input signal, and because frequency is the rate of change of phase, a loop that has locked phase has also locked frequency. That single mechanism does several distinct jobs across [[Telecommunications|telecommunications]] and computing, depending on what sits in the feedback path: with a divider it becomes a frequency synthesizer that multiplies a stable reference up to a new frequency; with no divider it becomes a tracking filter that recovers a clean, synchronized copy of a noisy or gapped input, as in clock recovery from a data stream; and run against a fixed reference it becomes a demodulator, since the control voltage that keeps a [[Frequency_modulation|frequency-modulated]] carrier locked is itself the demodulated signal. This article carries the Phase-locked loop sketch, which animates the loop's three-block ring on one oscilloscope-style display: the reader sets how far the input frequency sits from the oscillator's free-running frequency and how much loop gain is available to pull it in, switches between two loop designs, and watches the loop either settle into lock or slip cycles when the offset is too large to catch. ## Simple example Setting a clock once from a reliable time signal and then letting it run on its own is an open-loop correction: it fixes the phase at that instant but does nothing about a difference in rate, so the two clocks drift apart again immediately afterward. A phase-locked loop instead behaves like continually comparing a clock against the time signal and nudging the clock's rate, not just its reading, by an amount proportional to how far out of step it currently is. Because the correction acts on the rate, a persistent difference in phase turns into a persistent nudge that keeps shrinking it, and once the two are in step, matching rates, no further correction is needed, and the loop holds the clock there against the small disturbances the analogy below calls the same "sympathy" Huygens described in his pendulums. ## History Weakly coupled oscillators pulling each other into step is a far older observation than electronics: in February 1665 Christiaan Huygens reported to a fellow member of the Royal Society that two pendulum clocks hanging from the same beam in his room had fallen into a persistent "odd kind of sympathy," swinging in exact opposition however he disturbed them, an early documented case of the entrainment that a phase-locked loop later reproduces deliberately and by design rather than through incidental mechanical coupling.[^huygens1665] The electronic circuit is usually dated to 1932, when the French engineer Henri de Bellescize published a synchronous-reception scheme in which a receiver's local oscillator was locked to an incoming carrier's phase rather than merely tuned near its frequency, the earliest description of what is recognizably a phase-locked loop.[^debellescize32] Vacuum-tube phase-locked loops followed through the 1930s, used chiefly for [[Synchronization|synchronizing]] the horizontal and vertical sweep of early television receivers to a broadcast signal.[^schweber26] The technique moved onto a single [[Integrated_circuit|integrated circuit]] in 1969, when Signetics introduced the NE565 as a general-purpose monolithic phase-locked loop, one of the first integrated circuits sold explicitly as a complete loop rather than as parts a designer would assemble into one; the part's commercial success helped make the phase-locked loop a standard building block of analog and, later, digital design.[^schweber26] ## Structure and function Every phase-locked loop is built from the same three blocks arranged in a ring under [[Negative_feedback|negative feedback]]: a phase detector that compares the input against the loop's own oscillator, a filter that turns that comparison into a smooth control signal, and a voltage-controlled [[Harmonic_oscillator|oscillator]] that the control signal steers. Variations mostly change what implements each block: an analog loop uses a continuous phase detector and an op-amp filter, a digital loop replaces the phase detector with a logic circuit and often the filter with a [[Digital_filter|digital filter]], and an all-digital loop replaces the oscillator itself with a counter driven by a fixed clock, trading analog noise performance for a design that a standard digital process can fabricate directly alongside logic. A working loop is described by a handful of performance parameters. The hold range is the largest input-to-free-running frequency offset the loop can sustain once locked; the capture range, generally narrower, is the offset within which the loop will pull itself into lock from a cold start rather than slip cycles first; the lock time is how long acquisition takes; and phase noise and jitter describe how much the locked output still wanders from perfect phase tracking, set by the oscillator's own noise and by how much of the input's noise the loop's bandwidth lets through. ## Applications Because the same ring of blocks can be pointed at almost any repetitive signal, phase-locked loops appear throughout radio and digital electronics. In clock recovery a loop reconstructs a synchronized clock from a data stream that carries no separate clock line, by locking to the data's own transitions; a closely related use, deskewing, aligns the phase of a clock arriving at different points of a large digital chip so that every block switches together. Clock generation and clock distribution use a loop, often with a divider in the [[Feedback|feedback]] path, to multiply a single stable reference up to the many frequencies a system needs and to fan that timing out with a controlled phase relationship; deliberately dithering the divider ratio, in spread-spectrum clocking, spreads a digital clock's radiated energy across a small band of frequencies to reduce the height of any one interference peak. A loop locked to a carrier recovers that carrier's phase for coherent [[Amplitude_modulation|AM detection]], filters jitter and noise from a noisy reference by virtue of its own limited bandwidth, and, fitted with a feedback divider, performs frequency synthesis, generating the stable, selectable local-oscillator frequency a [[Superheterodyne_receiver|superheterodyne receiver]] tunes with. The same carrier-tracking role, used as a phase angle reference, lets a spacecraft-tracking receiver extract a distant transmitter's carrier phase from a signal far too weak to detect any other way, exactly the function a digital phase-locked loop performs inside NASA's Deep Space Network receivers as they track a spacecraft's Doppler-shifted carrier.[^jpldsn22] ## Block diagram Drawn as a block diagram, a phase-locked loop is a ring, not a chain: the phase detector's output feeds the filter, the filter's output steers the oscillator, and the oscillator's own output is fed back into the phase detector alongside the external input, closing the loop. Where the loop's job is to output a frequency that is a multiple of its input rather than equal to it, a frequency divider is inserted in that feedback path, between the oscillator and the phase detector, so that the detector compares the input against a divided-down copy of the output and the loop settles wherever that division makes the two match. ## Elements The phase detector compares the input and feedback phases and outputs a signal that grows with their difference; an analog multiplier-type detector produces a term proportional to the sine of the phase error once the comparison's double-frequency component has been filtered away, while a digital phase-frequency detector, built from a pair of [[Flip-flop_(electronics)|flip-flops]], additionally senses which input is leading and can pull the loop toward lock even from a large initial frequency error that a simple multiplier could not resolve. The filter sets the loop's dynamics from that raw comparison. A filter that is a pure gain gives what is usually called a type-1 loop: simple, but left with a small, permanent phase error once locked, because a steady control voltage is needed to hold the oscillator away from its free-running frequency and only a steady phase error can supply one. Adding an integrating term, a proportional-plus-integral filter much like the PI half of a [[PID_controller|PID controller]], gives a type-2 loop, in which the integrator itself supplies whatever steady control voltage is needed and drives the residual phase error to zero, at the cost of an overshoot that a damping parameter in the design controls. The oscillator, almost always a voltage-controlled oscillator, runs at a free-running frequency when its control [[Voltage|voltage]] is zero and shifts frequency in proportion to that input; because phase is the running integral of frequency, driving the oscillator's frequency is how the loop ultimately drives its phase into agreement with the input. The feedback path returns a sample of the oscillator's output to the phase detector, and an optional divider in that path, described above, is what turns a phase-locked loop from a pure tracking filter into a frequency synthesizer. ## Modeling Written as a differential equation for the loop's own oscillator phase, a phase-locked loop obeys a single first-order nonlinear equation once its carrier frequency is subtracted out: the phase error's rate of change equals the input's frequency offset from the oscillator's free-running frequency, minus the loop gain times the sine of the phase error itself, `d(phase_error)/dt = freq_offset - gain*sin(phase_error)`. A steady lock is a value of the phase error at which that rate is zero, which requires the sine of the phase error to equal the frequency offset divided by the gain; because a sine cannot exceed one in magnitude, a steady lock exists only when the frequency offset is no larger than the gain, the loop's hold range, and the corresponding steady phase error grows toward plus or minus ninety degrees as the offset approaches that limit. Push the offset past the gain and no steady point remains: the phase error runs continuously instead of settling, the loop is said to slip cycles, and the input and the oscillator beat against each other rather than locking. For small phase errors the sine is well approximated by the angle itself, and the same equation linearizes into an ordinary first- or second-order linear system depending on whether the loop is type-1 or type-2, which is what lets standard control-theory tools such as the [[Transfer_function|transfer function]] and the [[Nyquist_stability_criterion|Nyquist stability criterion]] be applied to loop design in place of the full nonlinear equation; a type-2 loop's linearized response is characterized, as with any second-order system, by a natural frequency and a [[Damping|damping]] ratio that together set how quickly it acquires lock and how much it overshoots on the way. Implementing a digital phase-locked loop in software or in [[Digital_signal_processing|digital hardware]] means integrating this same equation on a fixed [[Sampling_(signal_processing)|sample]] clock rather than continuously, which is exactly the numerical scheme the sketch on this page uses, advancing both the input and oscillator phase by a fixed timestep, split into several substeps per animation frame for numerical stability. ## Microsims The Phase-locked loop sketch draws the loop as a labeled ring of three blocks and drives four linked panels from a single running simulation. A live oscilloscope trace plots the sine of the input phase against the sine of the oscillator's own phase, so a locked loop shows two steady, aligned waves and an unlocked one visibly slips against the other; three scrolling strips below it track the phase error and the two instantaneous frequencies over time, and an analytic S-curve panel plots the sine of the phase error itself, with a horizontal line marking the frequency offset divided by the gain and a moving dot marking where the loop currently sits on that curve, on the stable or the unstable branch. Sliders set the frequency offset, the loop gain, shown as the hold range it implies, and, for the type-2 design, the damping; number keys switch between the type-1 and type-2 loop filters described above, and other keys step the input frequency or reset the loop from scratch. A status line reports whether the loop is locked, still acquiring, or, once the offset exceeds the hold range, slipping cycles outright. *Try:* Switch the sketch to the type-1 loop, raise the frequency offset slider until the status line reports the loop is slipping cycles, then switch to type-2 with the same offset and watch the extra integrator pull it back into a steady lock with no leftover phase error. A three.js companion sim renders this same second-order loop in more depth, plotting the phase error against time through capture, lock and tracking.  **Microsim — three.js (Wikitube framework), pending deploy:** *Phase-locked loop: capture, lock, and track* will play here once `https://wikitube-3d-microsims.netlify.app/signal/Phase-locked_loop.html` is live.  *Built from `MICROSIM_GUIDE/specs/sims/Phase-locked_loop.json`; part of the [[Signal_processing]] set ([[PORTAL_Signal_Processing]]).*  ## Wikipedia : Wikitube **Strict pair:** [Wikipedia](https://en.wikipedia.org/wiki/Phase-locked_loop) : [Wikitube](https://en.wikitube.io/wiki/Phase-locked_loop) Skeleton mirrored at revision 1371852065. Prose, emphasis and the microsims are Wikitube's own. ## See also - [[Superheterodyne_receiver]] - [[Frequency_modulation]] - [[Christiaan_Huygens]] - [[Negative_feedback]] - [[Control_theory]] - [[Kalman_filter]] - [[Synchronization]] ## Notes The sketch is ILLUSTRATIVE: it integrates the reduced, carrier-free phase-error equation given above rather than a transistor- or gate-level circuit, and its type-1/type-2 toggle idealizes the loop filter as either a pure gain or an ideal proportional-plus-integral network, leaving out the extra, higher-order poles a real filter would add. ## References The negative-feedback ring, the phase-error differential equation and its linearization, and the classification of loops by filter type are standard results in control theory and are not separately footnoted here, per Wikitube style guide §6.1. The items below ground the article's names, dates and specific claims. [^huygens1665]: Peña Ramírez, J.; Olvera, L. A.; Nijmeijer, H.; Alvarez, J. "The sympathy of two pendulum clocks: beyond Huygens' observations." *Scientific Reports*, vol. 6, article 23580, 2016. DOI: https://doi.org/10.1038/srep23580 [^debellescize32]: de Bellescize, H. "La réception synchrone." *L'Onde Électrique*, vol. 11, 1932. https://books.google.com/books/about/La_r%C3%A9ception_synchrone.html?id=8UJENwAACAAJ [^schweber26]: Schweber, B. "Basics of phase-locked loops, from analog-only to all-digital: part 1." *5G Technology World*, September 14, 2026. https://www.5gtechnologyworld.com/basics-of-phase-locked-loops-from-analog-only-to-all-digital-part-1/ [^jpldsn22]: Jet Propulsion Laboratory. "Deep Space Network: Doppler Tracking." DSN document 810-005, module 202, rev. E, July 19, 2022. https://deepspace.jpl.nasa.gov/dsndocs/810-005/202/202E.pdf ## Further reading - Steven Ellingson. *Radio Systems Engineering*, Revised First Edition (2023). Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/radio-systems-engineering - Don Johnson. *Fundamentals of Electrical Engineering I* (2014). Open Textbook Library: https://open.umn.edu/opentextbooks/textbooks/fundamentals-of-electrical-engineering-1 ## External links - Phase-locked loop, live sketch: https://editor.p5js.org/sciencenibber/full/1LQddWMci - Phase-locked loop, editor fork: https://editor.p5js.org/sciencenibber/sketches/1LQddWMci