Very-large-scale_integration

# Very-large-scale integration ## Microsim (three.js) <div class="microsim-player">  <p class="wt-pending"><strong>Microsim staged, not yet on the CDN.</strong> <code>Very-large-scale_integration.html</code> is built and deploy-ready in <code>Microsims for Dissemination/</code>, but the Netlify project still serves the geometry+spintronics set only. The player is disabled until the deploy lands; the explanatory text below is unchanged.</p>   </div> *A single silicon die is where the abstract Boolean circuit logic of the ALGORITHM hub turns into physical matter: very-large-scale integration is the fabrication substrate beneath every Central processing unit and [[Graphics_processing_unit]], and the bridge that carries [[Computer_architecture]] down to switching transistors.* > Very-large-scale integration (VLSI) is the practice of packing millions to billions of transistors onto one integrated circuit. A working chip spans about seven orders of magnitude in size — from a centimetre-wide die to nanometre transistor gates — so no single view can hold all of it. This microsim turns that span into one continuous zoom: sliding inward carries you from the whole packaged chip, through functional blocks and cell rows, down to individual gates and single transistors. Each stop is a different level of design abstraction, so the journey makes the hierarchy visible. ## About this microsim The sim exposes exactly one control, **zoomSlider**, running from 0 to 300, which drives a single continuous magnification of a stylised VLSI die. At the low end the whole chip and its package fill the frame; as you push toward 300 the view magnifies and finer structure resolves — coarse functional blocks (a processor core, a cache array, I/O pads) give way to rows of standard cells, then to individual gates, and near the top of the range to single transistors and the metal interconnect that wires them together. Because there is only one slider and one axis of change, the sim isolates a single idea: **scale**. Sweeping it slowly *is* the experiment — you watch abstraction levels emerge and dissolve into one another, and you feel how much structure hides inside one square millimetre of silicon. ## Related microsims - Register-transfer level — the abstraction one step above the gates you zoom into - Logic synthesis — compiles RTL into the gate netlist laid out on the die - Hardware description language — the Verilog/VHDL source a VLSI flow consumes - Central processing unit — the largest functional block you meet mid-zoom - CPU cache — the regular memory array that resolves as you descend - Three-dimensional integrated circuit — stacking dies to beat 2-D scaling limits - Complex programmable logic device — related ALGORITHM microsim - [[Computer_hardware]] — related ALGORITHM microsim - Macrocell array — related ALGORITHM microsim - Memory cell (computing) — related ALGORITHM microsim - Programmable logic array — related ALGORITHM microsim - Programmable logic device — related ALGORITHM microsim - Sheffer stroke — related ALGORITHM microsim - Switching circuit theory — related ALGORITHM microsim - Tensor Processing Unit — related ALGORITHM microsim - Transport triggered architecture — related ALGORITHM microsim ## Links (Wikipedia order)  `ACM_Computing_Classification_System` · `Abutment` · [[Algorithm]] · [[Algorithmic_efficiency]] · `Amdahl's_law` · `Analysis_of_algorithms` · `Application-specific_integrated_circuit` · `Application_security` · [[Artificial_intelligence]] · [[Augmented_reality]] · `Automata_theory` · `Automated_planning_and_scheduling` · `Bell_Labs` · `Capacitor` · `Carver_Mead` · `Clock_skew` · [[Communication_protocol]] · `Computability_theory` · `Computational_biology` · `Computational_chemistry` · `Computational_complexity` · `Computational_complexity_theory` · `Computational_engineering` · `Computational_geometry` · `Computational_intelligence` · `Computational_mathematics` · `Computational_physics` · `Computational_problem` · `Computational_social_science` · `Computer_History_Museum` · `Computer_accessibility` · `Computer_animation` · [[Computer_architecture]] · `Computer_data_storage` · `Computer_graphics` · [[Computer_hardware]] · `Computer_network` · [[Computer_science]] · `Computer_security` · `Computer_vision` · `Computing` · `Computing_platform` · `Concurrency_(computer_science)` · `Concurrent_computing` · `Control_flow` · [[Control_theory]] · `Cross-validation_(statistics)` · `Cryptography` · `Cyber-physical_system` · `Cyberwarfare` · `Data_mining` · `Database` · `Decision_support_system` · [[Dependability]] · `Design_closure` · `Design_for_X` · `Design_rule_checking` · `Die_(integrated_circuit)` · `Digital_art` · [[Digital_library]] · `Digital_marketing` · `Diode` · `Discrete_mathematics` · `Distributed_artificial_intelligence` · `Distributed_computing` · `Document_management_system` · `Domain-specific_language` · `Doping_(semiconductor)` · `E-commerce` · `Educational_technology` · `Electronic_circuit` · `Electronic_design_automation` · `Electronic_publishing` · `Electronic_voting` · `Embedded_system` · `Enterprise_information_system` · `Enterprise_software` · `Extended_reality` · [[Fault_tolerance]] · `Form_factor_(design)` · `Formal_language` · `Formal_methods` · `General_Micro-electronics` · `Geographic_information_system` · `Glue_logic` · [[Graphics_processing_unit]] · `Green_computing` · `Hardware_acceleration` · `Hardware_description_language` · `Hardware_security` · `Health_informatics` · `History_of_the_transistor` · `Human-centered_computing` · `Human–computer_interaction` · [[Image_compression]] · [[Industrial_process_control]] · `Information_retrieval` · `Information_security` · [[Information_system]] · [[Information_theory]] · `Integrated_circuit` · `Integrated_circuit_layout` · `Integrated_development_environment` · `Interaction_design` · `Interface_logic_model` · `Interpreter_(computing)` · `Intrusion_detection_system` · `Invention_of_the_integrated_circuit` · `Jack_Kilby` · `Knowledge_representation_and_reasoning` · `Library_(computing)` · `List_of_computer_size_categories` · [[Logic_gate]] · `Logic_in_computer_science` · `Logic_synthesis` · `Lynn_Conway` · [[Machine_learning]] · `Mathematical_analysis` · [[Mathematical_optimization]] · [[Mathematical_software]] · `Microprocessor` · `Middleware` · `Mobile_computing` · `Model_of_computation` · `Modeling_language` · `Moore's_law` · `Multi-task_learning` · `Multimedia_database` · [[Multiprocessing]] · [[Multithreading_(computer_architecture)]] · `Natural_language_processing` · `Network_architecture` · `Network_performance` · `Network_scheduler` · `Network_security` · `Network_service` · `Networking_hardware` · `Numerical_analysis` · `Open_source` · `Operating_system` · [[Operations_research]] · `Outline_of_computer_science` · `Parallel_computing` · `Peripheral` · `Philosophy_of_artificial_intelligence` · `Photograph_manipulation` · `Photolithography` · `Photomask` · `Polycrystalline_silicon` · `Printed_circuit_board` · [[Probability]] · `Processor_(computing)` · `Programming_language` · `Programming_language_theory` · `Programming_paradigm` · `Programming_team` · `Programming_tool` · [[Quantum_computing]] · `Randomized_algorithm` · [[Real-time_computing]] · [[Reinforcement_learning]] · `Rendering_(computer_graphics)` · `Requirements_analysis` · `Resistor` · `Robert_Noyce` · `Routing_(electronic_design_automation)` · `Security_hacker` · `Security_service_(telecommunication)` · `Semiconductor` · `Social_computing` · `Social_software` · `Software_configuration_management` · `Software_construction` · `Software_deployment` · `Software_design` · `Software_development` · `Software_development_process` · [[Software_engineering]] · `Software_framework` · `Software_maintenance` · [[Software_quality]] · `Software_repository` · `Solid_modeling` · `Static_random-access_memory` · `Statistics` · `Stochastic_computing` · `Structured_programming` · `Supervised_learning` · `System_on_a_chip` · [[Telecommunications]] · `Theoretical_computer_science` · `Theory_of_computation` · [[Transistor]] · `Ubiquitous_computing` · `Unsupervised_learning` · `Video_game` · `Virtual_machine` · [[Virtual_reality]] · `Visualization_(graphics)` · `Wafer_(electronics)` · [[Wayback_Machine]] · `Wireless_sensor_network` · `Word_processor` · `World_Wide_Web` ## Overview VLSI emerged in the mid-1970s, when photolithography could place tens of thousands of transistors on a chip, surpassing the earlier SSI, MSI, and LSI regimes (small-, medium-, and large-scale integration: tens, hundreds, and thousands of devices). Carver Mead and Lynn Conway's 1980 text *Introduction to VLSI Systems* codified a structured, scalable design methodology that made such complexity manageable. Growth has tracked **Moore's Law** — Gordon Moore's 1965 observation that transistor count per chip doubles roughly every two years — carrying the field past a billion transistors on a single modern processor. Almost all VLSI is built in CMOS (complementary metal-oxide-semiconductor), which dissipates negligible static power. VLSI is, in short, the manufacturing reality behind essentially all modern digital hardware. ## The design hierarchy A chip is designed as a stack of abstraction levels, and the zoom journey visits them in order: | Magnification | Level | What lives here | |---|---|---| | lowest | System / die | package, pads, top-level floorplan | | low–mid | Architecture / RTL | functional blocks: cores, caches, buses | | mid | Logic (gate) | combinational and sequential netlists | | high | Circuit | transistor-level cells: inverters, NANDs | | highest | Device / physical | single MOSFETs, doped regions, metal layers | Designers work top-down: a chip is described in a Hardware description language at the Register-transfer level, then Logic synthesis compiles that into a netlist of Combinational logic and [[Sequential_logic]], and place-and-route tools map the gates onto physical layers. Two laws govern the descent. Moore's Law reads $N(t) = N_0 \, 2^{(t - t_0)/T}, \qquad T \approx 2\ \text{years},$ and dynamic switching power is $P = \alpha\, C\, V^2 f,$ with $\alpha$ the activity factor, $C$ the switched capacitance, $V$ the supply, and $f$ the Clock rate. Under classical Dennard scaling each linear dimension shrinks about $0.7\times$ per node, so area falls to $\approx 0.5$ and density doubles — which is why the view keeps getting denser as you zoom. ## Controls -> what each maps to | Control | Maps to | Range / values | Meaning | |---|---|---|---| | zoomSlider | Magnification / depth in the design hierarchy | 0–300 | 0 frames the whole packaged die; increasing the value zooms inward through blocks, cells, gates, and finally individual transistors and interconnect. | ## Learning objective After sweeping the slider, a learner can explain that a VLSI chip is a nested hierarchy — die, block, cell, gate, transistor — and predict which structures resolve as spatial scale changes. ## Limits and connections The sim shows scale and hierarchy, not behaviour: nothing switches and no logic evaluates, so it complements rather than replaces gate- or RTL-level simulators. Real design also unfolds in time (clocking, Metastability (electronics)) and varies with manufacturing, which a static zoom cannot capture. Escaping the two-dimensional floorplan pictured here is exactly the motivation for Three-dimensional integrated circuit stacking. ## Poster & source <div class="microsim-fallback">  <p><em>Live microsim · <a href="https://wikitube-3d-microsims.netlify.app/Very-large-scale_integration.html">open full</a> · source: Microsims for Dissemination/ALGORITHM_microsims/Very-large-scale_integration.html</em></p> </div>  *Built to the [[WT!Three_js_Microsim_Master_Class|three.js Master Class]].*  ## Wikipedia : Wikitube **Strict pair:** [Wikipedia](https://en.wikipedia.org/wiki/Very-large-scale_integration) : [Wikitube](https://en.wikitube.io/wiki/Very-large-scale_integration) ## Previous hub tags Tree parents: [[Graph_theory]] · [[Information_theory]]. Legacy hubs: `ALGORITHM`. --- *Sources: 1 legacy note. Minted wave 1, 2026-07-30 (v1.6 order).*